The present disclosure relates to a data transmission circuit and a semiconductor memory device including the same, and more particularly to a semiconductor memory device having a sense amplifier.
When a latch-type sense amplifier is used for speeding up a dynamic circuit including bit lines, design of a timing circuit that determines startup of the sense amplifier poses a major problem. That is, when the sense amplifier is started with no sufficient potential difference having occurred in the bit line pair, speedup may be achieved but the possibility of causing erroneous read increases. Conversely, when the sense amplifier is started after appearance of a large potential difference in the bit line pair, the possibility of causing erroneous read may decrease but no speedup is achieved.
To address the above problem, conventionally, the startup timing of a sense amplifier has been determined in the following manner. While the timing at which the speed of read from memory cells is lowest is predicted to secure a margin for preventing erroneous read, the delay timing of a delay circuit including inverters, etc. is set at design time so that the sense amplifier be started at high speed. However, the prediction of a necessary timing margin is becoming increasingly difficult because variations in the potential difference in the bit line pair are increasing due to variations among production lots, random variations in a chip, etc. caused by miniaturization. As a means for solving this problem, a technique is known where a voltage change in the bit line pair is detected to generate a startup signal for the sense amplifier automatically (see Japanese Patent Publication No. H6-84376 (Patent Document 1)).